Lessons In
Electric Circuits, Volume IV – Digital By Tony R. Kuphaldt Fourth Edition
Lessons In Electric Circuits, Volume IV – Digital By Tony R. Kuphaldt Fourth Edition, last update November 01, 2007
Contents
1 NUMERATION SYSTEMS 1
1.1 Numbers and symbols . . . . . . . . . 1
1.2 Systems of numeration . . . . . . . . . 6
1.3 Decimal versus binary numeration . . 8
1.4 Octal and hexadecimal numeration . 10
1.5 Octal and hexadecimal to decimal conversion . . . . . .
. . . . . . . . . . . . . . . 12
1.6 Conversion from decimal numeration . . . . . . . . . . .
. . . . . . . . . . . . . . 13
2 BINARY ARITHMETIC 19
2.1 Numbers versus numeration . . . . . 19
2.2 Binary addition . . . . . . . . . . . . . 20
2.3 Negative binary numbers . . . . . . . 20
2.4 Subtraction . . . . . . . . . . . . . . . 23
2.5 Overflow . . . . . . . . . . . . . . . . . 25
2.6 Bit groupings . . . . . . . . . . . . . . 27
3 LOGIC GATES 29
3.1 Digital signals and gates . . . . . . . 30
3.2 The NOT gate . . . . . . . . . . . . . . 33
3.3 The ”buffer” gate . . . . . . . . . . . . 45
3.4 Multiple-input gates . . . . . . . . . . 48
3.5 TTL NAND and AND gates . . . . . . 60
3.6 TTL NOR and OR gates . . . . . . . . 65
3.7 CMOS gate circuitry . . . . . . . . . . 68
3.8 Special-output gates . . . . . . . . . . 81
3.9 Gate universality . . . . . . . . . . . . 85
3.10 Logic signal voltage levels . . . . . . . 90
3.11 DIP gate packaging . . . . . . . . . . . 100
3.12 Contributors . . . . . . . . . . . . . . . 102
4 SWITCHES 103
4.1 Switch types . . . . . . . . . . . . . . . 103
4.2 Switch contact design . . . . . . . . . 108
4.3 Contact ”normal” state and make/break sequence . . . . .
. . . . . . . . . . . . . 111
iii
iv CONTENTS
4.4 Contact ”bounce” . . . . . . . . . . . . 116
5 ELECTROMECHANICAL RELAYS 119
5.1 Relay construction . . . . . . . . . . . 119
5.2 Contactors . . . . . . . . . . . . . . . . 122
5.3 Time-delay relays . . . . . . . . . . . . 126
5.4 Protective relays . . . . . . . . . . . . 132
5.5 Solid-state relays . . . . . . . . . . . . 133
6 LADDER LOGIC 135
6.1 ”Ladder” diagrams . . . . . . . . . . . 135
6.2 Digital logic functions . . . . . . . . . 139
6.3 Permissive and interlock circuits . . . 144
6.4 Motor control circuits . . . . . . . . . 147
6.5 Fail-safe design . . . . . . . . . . . . . 150
6.6 Programmable logic controllers . . . . 154
6.7 Contributors . . . . . . . . . . . . . . . 171
7 BOOLEAN ALGEBRA 173
7.1 Introduction . . . . . . . . . . . . . . . 173
7.2 Boolean arithmetic . . . . . . . . . . . 175
7.3 Boolean algebraic identities . . . . . . 178
7.4 Boolean algebraic properties . . . . . 181
7.5 Boolean rules for simplification . . . . 184
7.6 Circuit simplification examples . . . . 187
7.7 The Exclusive-OR function . . . . . . 192
7.8 DeMorgan’s Theorems . . . . . . . . . 193
7.9 Converting truth tables into Boolean expressions . . . .
. . . . . . . . . . . . . . 200
8 KARNAUGH MAPPING 219
8.1 Introduction . . . . . . . . . . . . . . . 219
8.2 Venn diagrams and sets . . . . . . . . 220
8.3 Boolean Relationships on Venn Diagrams . . . . . . . . .
. . . . . . . . . . . . . . 223
8.4 Making a Venn diagram look like a Karnaugh map . . . . .
. . . . . . . . . . . . 228
8.5 Karnaugh maps, truth tables, and Boolean expressions . .
. . . . . . . . . . . . . 231
8.6 Logic simplification with Karnaugh maps . . . . . . . .
. . . . . . . . . . . . . . . 238
8.7 Larger 4-variable Karnaugh maps . . 245
8.8 Minterm vs maxterm solution . . . . 249
8.9 (sum) and (product) notation . . . 261
8.10 Don’t care cells in the Karnaugh map . . . . . . . . .
. . . . . . . . . . . . . . . . 262
8.11 Larger 5 & 6-variable Karnaugh maps . . . . . . . .
. . . . . . . . . . . . . . . . 265
9 COMBINATIONAL LOGIC FUNCTIONS 273
9.1 Introduction . . . . . . . . . . . . . . . 273
9.2 A Half-Adder . . . . . . . . . . . . . . 274
9.3 A Full-Adder . . . . . . . . . . . . . . 275
CONTENTS v
9.4 Decoder . . . . . . . . . . . . . . . . . 282
9.5 Encoder . . . . . . . . . . . . . . . . . 286
9.6 Demultiplexers . . . . . . . . . . . . . 289
9.7 Multiplexers . . . . . . . . . . . . . . . 293
9.8 Using multiple combinational circuits . . . . . . . . .
. . . . . . . . . . . . . . . . 294
10 MULTIVIBRATORS 299
10.1 Digital logic with feedback . . . . . . 299
10.2 The S-R latch . . . . . . . . . . . . . . 303
10.3 The gated S-R latch . . . . . . . . . . 307
10.4 The D latch . . . . . . . . . . . . . . . 308
10.5 Edge-triggered latches: Flip-Flops . . 310
10.6 The J-K flip-flop . . . . . . . . . . . . . 315
10.7 Asynchronous flip-flop inputs . . . . . 317
10.8 Monostable multivibrators . . . . . . 319
11 SEQUENTIAL CIRCUITSCOUNTERS 323
11.1 Binary count sequence . . . . . . . . . 323
11.2 Asynchronous counters . . . . . . . . 325
11.3 Synchronous counters . . . . . . . . . 332
11.4 Counter modulus . . . . . . . . . . . . 338
11.5 Finite State Machines . . . . . . . . . 338
Bibliography . . . . . . . . . . . . . . . . . . 347
12 SHIFT REGISTERS 349
12.1 Introduction . . . . . . . . . . . . . . . 349
12.2 Serial-in/serial-out shift register . . . 352
12.3 Parallel-in, serial-out shift register . . 361
12.4 Serial-in, parallel-out shift register . 372
12.5 Parallel-in, parallel-out, universal shift register . .
. . . . . . . . . . . . . . . . . 381
12.6 Ring counters . . . . . . . . . . . . . . 392
12.7 references . . . . . . . . . . . . . . . . 405
13 DIGITAL-ANALOG CONVERSION 407
13.1 Introduction . . . . . . . . . . . . . . . 407
13.2 The R/2nR DAC . . . . . . . . . . . . . 409
13.3 The R/2R DAC . . . . . . . . . . . . . 412
13.4 Flash ADC . . . . . . . . . . . . . . . . 414
13.5 Digital ramp ADC . . . . . . . . . . . 417
13.6 Successive approximation ADC . . . . 419
13.7 Tracking ADC . . . . . . . . . . . . . . 421
13.8 Slope (integrating) ADC . . . . . . . . 422
13.9 Delta-Sigma () ADC . . . . . . . . 425
13.10Practical considerations of ADC circuits . . . . . . .
. . . . . . . . . . . . . . . . . 427
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14 DIGITAL COMMUNICATION 433
14.1 Introduction . . . . . . . . . . . . . . . 433
14.2 Networks and busses . . . . . . . . . . 437
14.3 Data flow . . . . . . . . . . . . . . . . . 441
14.4 Electrical signal types . . . . . . . . . 442
14.5 Optical data communication . . . . . 446
14.6 Network topology . . . . . . . . . . . . 448
14.7 Network protocols . . . . . . . . . . . 450
14.8 Practical considerations . . . . . . . . 453
15 DIGITAL STORAGE (MEMORY) 455
15.1 Why digital? . . . . . . . . . . . . . . . 455
15.2 Digital memory terms and concepts . 456
15.3 Modern nonmechanical memory . . . 458
15.4 Historical, nonmechanical memory technologies . . . . .
. . . . . . . . . . . . . . 460
15.5 Read-only memory . . . . . . . . . . . 466
15.6 Memory with moving parts: ”Drives” . . . . . . . . . .
. . . . . . . . . . . . . . . 467
16 PRINCIPLES OF DIGITAL COMPUTING 471
16.1 A binary adder . . . . . . . . . . . . . 471
16.2 Look-up tables . . . . . . . . . . . . . 472
16.3 Finite-state machines . . . . . . . . . 477
16.4 Microprocessors . . . . . . . . . . . . . 481
16.5 Microprocessor programming . . . . . 484
A-1 ABOUT THIS BOOK 487
A-2 CONTRIBUTOR LIST 493
A-3 DESIGN SCIENCE LICENSE 497
INDEX 500
