ANALYSIS AND
DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth EditionPAUL R. GRAY
University of California, Berkeley
PAUL J. HURST
University of California, Davis
STEPHEN H. LEWlS
University of California, Davis
ROBERT G. MEYER
University of California, Berkeley
Contents
.
CHAPTER l
Models for Integrated-Circuit Active
Devices 1
Introduction 1
Depletion Region of a pn Junction 1
1.2.1 Depletion-Region Capacitance 5
1.2.2 JunctionBreakdown 6
Large-Signal Behavior of Bipolar
Transistors 8
1.3.1 Large-Signal Models in the
Forward-Active Region 9
1.3.2 Effects of Collector Voltage on
Large-Signal Characteristics in the
Forward-Active Region 14
1.3.3 Saturation and Inverse Active
Regions 16
1.3.4 Transistor Breakdown Voltages
20
1.3.5 Dependence of Transistor Current
Gain PF on Operating Conditions
23
Small-Signal Models of Bipolar
Transistors 26
1.4.1 Transconductance 27
1.4.2 Base-Charging Capacitance 28
1.4.3 Input Resistance 29
1.4.4 Output Resistance 29
1.4.5 Basic Small-Signal Model of the
Bipolar Transistor 30
1.4.6 Collector-Base Resistance 30
1.4.7 Parasitic Elements in the
Small-Signal Model 3 1
1 A.8 Specification of Transistor
Frequency Response 34
Large Signal Behavior of
Metal-Oxide-Semiconductor
Field-Effect Transistors 38
1.5.1 Transfer Characteristics of MOS
1 S.2 Comparison of Operating Regions
of Bipolar and MOS Transistors
45
1 S.3 Decomposition of Gate-Source
Voltage 47
1.5.4 Threshold Temperature
Dependence 47
1.5.5 MOS Device Voltage Limitations
48
1.6 Small-Signal Models of the MOS
\/Transistors 49
1.6.1 Transconductance 50
1.6.2 Intrinsic Gate-Source and
Gate-Drain Capacitance 51
1.6.3 InputResistance 52
1.6.4 Output Resistance 52
1.6.5 Basic Small-Signal Model of the
MOS Transistor 52
1.6.6 Body Transconductance 53
1.6.7 Parasitic Elements in the
Small-Signal Model 54
1.6.8 MOS Transistor Frequency
Response 55
1.7 Short-Channel Effects in MOS
Transistors 58
1.7.1 Velocity Saturation from the
Horizontal Field 59
1.7.2 Transconductance and Transition
Frequency 63
1.7.3 Mobility Degradation from the
Vertical Field 65
1.8 Weak Inversion in MOS Transistors
65
1 .S. 1 Drain Current in Weak Inversion
66
1.8.2 Transconductance and Transition
Frequency in Weak Inversion 68
1.9 Substrate Current Flow in MOS
Transistors 7 1
A.
1.1 Summary of Active-Device
B.
CHAPTER 2
C.
Bipolar, MOS, and BiCMOS
D.
Integrated-Circuit Technology 78
E.
Introduction 78
F.
Basic Processes in Integrated-Circuit
G.
Fabrication 79
H.
Electrical Resistivity of Silicon
I.
79
J.
Solid-state Diffusion 80
K.
Electrical Properties of Diffused
L.
Layers 82
M.
Photolithography 84
N.
Epitaxial Growth 85
O.
Ion Implantation 87
P.
Local Oxidation 87
Q.
Polysilicon Deposition 87
R.
High-Voltage Bipolar
S.
Integrated-Circuit Fabrication 88
T.
Advanced Bipolar Integrated-Circuit
U.
Fabrication 92
V.
Active Devices in Bipolar Analog
W. Integrated
Circuits 95
X.
2.5.1 Integrated-Circuit npn Transistor
Y.
96
Z.
2.5.2 Integrated-Circuit pnp Transistors
AA.
107
BB.
Passive Components in Bipolar
CC.Integrated Circuits 115
DD.
2.6.1 Diffused Resistors 115
EE.2.6.2 Epitaxial and Epitaxial
Pinch
FF.Resistors 119
GG.
2.6.3 Integrated-Circuit Capacitors 120
HH.
2.6.4 Zener Diodes 121
II.
2.6.5 Junction Diodes 122
JJ. Modifications
to the Basic Bipolar
KK.
Process 123
LL.2.7.1
MM.
2.7.2
NN.
2.7.3
OO.
MOS
PP.127
QQ.
Dielectric Isolation 123
RR.
Compatible Processing for
SS. High-Performance
Active Devices
TT.124
UU.
High-Performance Passive
VV.
Components 127
WW.
Integrated-Circuit Fabrication
XX.
Active Devices in MOS Integrated
YY.Circuits 131
ZZ.2.9.1 n-Channel Transistors 13
1
AAA.
2.9.2 p-Channel Transistors 14 1
BBB.
2.9.3 Depletion Devices 142
CCC.
2.9.4 Bipolar Transistors 142
DDD.
Passive Components in MOS
EEE.
Technology 144
FFF.
2.10.1 Resistors 144
GGG.
2.10.2 Capacitors in MOS Technology
HHH.
145
III. 2.10.3
Latchup in CMOS Technology
JJJ.
148
KKK.
BiCMOS Technology 150
LLL.
Heterojunction Bipolar Transistors
MMM.
152
NNN.
Interconnect Delay 153
OOO.
Economics of Integrated-Circuit
PPP.
Fabrication 154
QQQ.
2.14.1 Yield Considerations in
RRR.
Integrated-Circuit Fabrication
SSS.
154
TTT.
2.14.2 Cost Considerations in
UUU.
Integrated-Circuit Fabrication
VVV.
157
WWW.
Packaging Considerations for
XXX.
Integrated Circuits 159
YYY.
2.15.1 Maximum Power Dissipation 159
ZZZ.
2.15.2 Reliability Considerations in
AAAA.
Integrated-Circuit Packaging 162
BBBB.
A.2.1 SPICE Model-Parameter Files 163
CCCC.
CHAPTER 3
DDDD.
Single-Transistor and Multiple-Transistor
EEEE.
Amplifiers 170
FFFF.
3.1 Device Model Selection for
GGGG.
Approximate Analysis of Analog
HHHH.
Circuits 171
IIII.
3.2 Two-Port Modeling of Amplifiers 172
JJJJ.
3.3 Basic Single-Transistor Amplifier
KKKK.
Stages 174
LLLL.
3.3.1 Common-Emitter Configuration
MMMM.
175
NNNN.
3.3.2 Common-Source Configuration
OOOO.
179
PPPP.
3.3.3 Common-Baseconfiguration 183
QQQQ.
3.3.4 Common-Gate Configuration 186
RRRR.
xii Contents
SSSS.
3.3.5 Common-Base and Common-Gate
TTTT.
Configurations with Finite r, 188
UUUU.
3.3.5.1 Common-Base and
VVVV.
Common-Gate Input
WWWW. Resistance
188
XXXX.
3.3.5.2 Common-Base and
YYYY.
Common-Gate Output
ZZZZ.
Resistance 190
AAAAA.
3.3.6 Common-Collector Configuration
BBBBB.
(Emitter Follower) 19 1
CCCCC.
3.3.7 Common-Drain Configuration
DDDDD.
(Source Follower) 195
EEEEE.
3.3.8 Common-Emitter Amplifier with
FFFFF.
Emitter Degeneration 197
GGGGG.
3.3.9 Common-Source Amplifier with
HHHHH.
Source Degeneration 200
IIIII.
3.4 Multiple-Transistor Amplifier Stages
JJJJJ.
The CC-CE, CC-CC, and
KKKKK.
Darlington Configurations 202
LLLLL.
The Cascode Configuration 206
MMMMM.
3.4.2.1 The Bipolar Cascode 206
NNNNN.
3.4.2.2 The MOS Cascode 208
OOOOO.
The Active Cascode 211
PPPPP.
The Super Source Follower 213
QQQQQ.
3.5 Differential Pairs 215
RRRRR.
The dc Transfer Characteristic of
SSSSS.
an Emitter-Coupled Pair 2 15
TTTTT.
The dc Transfer Characteristic with
UUUUU.
Emitter Degeneration 2 17
VVVVV.
The dc Transfer Characteristic of a
WWWWW.
Source-Coupled Pair 2 18
XXXXX.
Introduction to the Small-Signal
YYYYY.
Analysis of Differential Amplifiers
ZZZZZ.
22 1
AAAAAA. Small-Signal
Characteristics of
BBBBBB. Balanced
Differential Amplifiers
CCCCCC.
224
DDDDDD.
Device Mismatch Effects in
EEEEEE.
Differential Amplifiers 23 1
FFFFFF.
Input Offset Voltage and
GGGGGG.
Current 23 1
HHHHHH.
Input Offset Voltage of
IIIIII.
the Emitter-Coupled Pair
JJJJJJ.
232
KKKKKK. Offset
Voltage of the
LLLLLL.
Emitter-Coupled Pair:
MMMMMM.
Approximate Analysis
NNNNNN.
232
OOOOOO.
Offset Voltage Drift in
PPPPPP.
the Emitter-Coupled Pair
QQQQQQ.
234
RRRRRR. 3.5.6.5
Input Offset Current
>>>>>>>>>>>>>>>>>TO<<<<<<<<<<<<<<,
CHAPTER 12
Fully Differential Operational Amplifiers
80 8
12.1 Introduction 808
12.2 Properties of Fully Differential
Amplifiers 808
12.3 Small-Signal Models for Balanced
Differential Amplifiers 8 11
12.4 Common-Mode Feedback 8 l6
12.4.1 Common-Mode Feedback at Low
Frequencies 8 17
12.4.2 Stability and Compensation
Considerations in a CMFB Loop
822
12.5 CMFB Circuits 823
12.5.1 CMFB Using Resistive Divider
and Amplifier 824
12.5.2 CMFB Using Two Differential
Pairs 828
12.5.3 CMFB Using Transistors in the
Triode Region 830
12.5.4 Switched-Capacitor CMFB 832
12.6 Fully Differential Op Amps 835
12.6.1 A Fully Differential Two-Stage Op
Amp 835
12.6.2 Fully Differential Telescopic
Cascode Op Amp 845
12.6.3 Fully Differential Folded-Cascode
Op Amp 846
12.6.4 A Differential Op Amp with Two
Differential Input Stages 847
12.6.5 Neutralization 849
12.7. Unbalanced Fully Differential
Circuits
850
12.8 Bandwidth of the CMFB Loop 856
Index 865
