Analysis And Design Of Analog Integrated Circuits
Fourth Edition PAUL R. GRAY
University of California, Berkeley
PAUL J. HURST
University of California, Davis
STEPHEN H. LEWIS
University of California, Davis
ROBERT G. MEYER
University of California, Berkeley
Contents
CHAPTER 1
Models for Integrated-Circuit Active
Devices 1
1.1 Introduction 1
1.2 Depletion Region of a pn Junction 1
1.2.1 Depletion-Region Capacitance 5
1.2.2 JunctionBreakdown 6
1.3 Large-Signal Behavior of Bipolar
Transistors 8
1.3.1 Large-Signal Models in the
Forward-Active Region 9
1.3.2 Effects of Collector Voltage on
Large-Signal Characteristics in the
Forward-Active Region 14
1.3.3 Saturation and Inverse Active
Regions 16
1.3.4 Transistor Breakdown Voltages
20
1.3.5 Dependence of Transistor Current
Gain PF on Operating Conditions
23
1.4 Small-Signal Models of Bipolar
Transistors 26
1.4.1 Transconductance 27
1.4.2 Base-Charging Capacitance 28
1.4.3 Input Resistance 29
1.4.4 Output Resistance 29
1.4.5 Basic Small-Signal Model of the
Bipolar Transistor 30
1.4.6 Collector-Base Resistance 30
1.4.7 Parasitic Elements in the
Small-Signal Model 3 1
1.4.8 Specification of Transistor
Frequency Response 34
1.5 Large Signal Behavior of
Metal-Oxide-Semiconductor
Field-Effect Transistors 38
1.5.1 Transfer Characteristics of MOS
Devices 38
1 .5.2 Comparison of Operating Regions
of Bipolar and MOS Transistors
45
1 .5.3 Decomposition of Gate-Source
Voltage 47
1.5.4 Threshold Temperature
Dependence 47
1.5.5 MOS Device Voltage Limitations
48
1.6 Small-Signal Models of the MOS
\/Transistors 49
1.6.1 Transconductance 50
1.6.2 Intrinsic Gate-Source and
Gate-Drain Capacitance 51
1.6.4 Output Resistance 52
1.6.5 Basic Small-Signal Model of the
MOS Transistor 52
1.6.6 Body Transconductance 53
1.6.7 Parasitic Elements in the
Small-Signal Model 54
1.6.8 MOS Transistor Frequency
Response 55
1.7 Short-Channel Effects in MOS
Transistors 58
1.7.1 Velocity Saturation from the
Horizontal Field 59
1.7.2 Transconductance and Transition
Frequency 63
1.7.3 Mobility Degradation from the
Vertical Field 65
1.8 Weak Inversion in MOS Transistors
65
1.8.1 Drain Current in Weak Inversion
66
1.8.2 Transconductance and Transition
Frequency in Weak Inversion 68
1.9 Substrate Current Flow in MOS
Transistors 7 1
A. 1.1 Summary of Active-Device
Parameters 73
CHAPTER 2
Bipolar, MOS, and BiCMOS
Integrated-Circuit Technology 78
2.1 Introduction 78
2.2 Basic Processes in Integrated-Circuit
Fabrication 79
2.2.1 Electrical Resistivity of Silicon
79
2.2.2 Solid-State Diffusion 80
2.2.3 Electrical Properties of Diffused
Layers 82
2.2.4 Photolithography 84
2.2.5 Epitaxial Growth 85
2.2.6 Ion Implantation 87
2.2.7 Local Oxidation 87
2.2.8 Polysilicon Deposition 87
2.3 High-Voltage Bipolar
Integrated-Circuit Fabrication 88
2.4 Advanced Bipolar Integrated-Circuit
Fabrication 92
2.5 Active Devices in Bipolar Analog
Integrated Circuits 95
2.5.1 Integrated-Circuit npn Transistor
96
2.5.2 Integrated-Circuit pnp Transistors
107
I
2.6 Passive Components in Bipolar
Integrated Circuits 115
2.6.1 Diffused Resistors 115
2.6.2 Epitaxial and Epitaxial Pinch
Resistors 119
2.6.3 Integrated-Circuit Capacitors 120
2.6.4 Zener Diodes 121
2.6.5 Junction Diodes 122
I 2.7 Modifications to the Basic Bipolar
I Process 123
2.7.1 Dielectric Isolation 123
2.7.2 Compatible Processing for
High-Performance Active Devices
124
2.7.3 High-Performance Passive
Components 127
2.8 MOS Integrated-Circuit Fabrication
127
2.9 Active Devices in MOS Integrated
4 Circuits 131
2.9.1 n-Channel Transistors 13 1
2.9.2 p-Channel Transistors 14 1
2.9.3 Depletion Devices 142
2.9.4 Bipolar Transistors 142
2.10 Passive Components in MOS
Technology 144
2.10.1 Resistors 144
2.10.2 Capacitors in MOS Technology
145
2.10.3 Latchup in CMOS Technology
148
2.11 BiCMOS Technology 150
2.12 Heterojunction Bipolar Transistors
152
2.13 Interconnect Delay 153
2.14 Economics of Integrated-Circuit
Fabrication 154
2.14.1 Yield Considerations in
Integrated-Circuit Fabrication
154
2.14.2 Cost Considerations in
Integrated-Circuit Fabrication
157
2.15 Packaging Considerations for
Integrated Circuits 159
2.15.1 Maximum Power Dissipation 159
2.15.2 Reliability Considerations in
Integrated-Circuit Packaging 162
A.2.1 SPICE Model-Parameter Files 163
CHAPTER 3
Single-Transistor and Multiple-Transistor
Amplifiers 170
3.1 Device Model Selection for
Approximate Analysis of Analog
Circuits 171
3.2 Two-Port Modeling of Amplifiers 172
3.3 Basic Single-Transistor Amplifier
Stages 174
3.3.1 Common-Emitter Configuration
175
3.3.2 Common-Source Configuration
179
3.3.3 Common-Baseconfiguration 183
3.3.4 Common-Gate Configuration 186
>>>>TO<<<
CHAPTER 12
Fully Differential Operational Amplifiers
80 8
12.1 Introduction 808
12.2 Properties of Fully Differential
Amplifiers 808
12.3 Small-Signal Models for Balanced
Differential Amplifiers 8 11
I 12.4 Common-Mode Feedback 8 16
12.4.1 Common-Mode Feedback at Low
Frequencies 8 17
12.4.2 Stability and Compensation
Considerations in a CMFB Loop
822
12.5 CMFB Circuits 823
12.5.1 CMFB Using Resistive Divider
and Amplifier 824
12.5.2 CMFB Using Two Differential
Pairs 828
12.5.3 CMFB Using Transistors in the
Triode Region 830
12.5.4 Switched-Capacitor CMFB 832
12.6 Fully Differential Op Amps 835
12.6.1 A Fully Differential Two-Stage Op
12.6.2 Fully Differential Telescopic
Cascode Op Amp 845
12.6.3 Fully Differential Folded-Cascode
Op Amp 846
12.6.4 A Differential Op Amp with Two
Differential Input Stages 847
12.6.5 Neutralization 849
12.7. Unbalanced Fully Differential Circuits
12.8 Bandwidth of the CMFB Loop 856
Index 865
